1. Technical Field
This disclosure generally relates to analog-to-digital converters and more specifically to sub-quantizer architectures for analog-to-digital converters.
2. Description of the Related Art
Common design architectures for analog to digital converters (ADCs) are the so-called “pipelined architectures.” For many applications, a pipelined architecture scheme is preferable because it provides optimum power dissipation characteristics. In addition, there are other available architectures that resemble a pipelined architecture because the same principle building blocks are employed.
FIG. 1 illustrates a typical pipelined ADC. The architecture consists of several pipeline stages, each resolving a number of bits. The number of bits can be different for each stage, but for simplicity of explanation, all stages are considered equal. The input signal is applied to the first pipeline stage. A number of bits are extracted in the first stage by the sub-ADC, the input signal is sampled in parallel and the analog value corresponding to the output bits is subtracted from the input voltage. The residual signal, called the “residue,” is amplified with a factor dependent on the number of bits extracted and passed on to the next stage. The process is repeated in the consecutive stages. The digital output from each stage is processed in a digital correction logic block and combined into an n-bit output data word.
Several prior art techniques have been used to improve power dissipation of pipelined ADCs. The two papers explain a technique that is shown to significantly reduce power dissipation: (1) Gupta et al., A 1GS/s 11b Time-Interleaved ADC in 0.13 um CMOS, 2006 Digest of Technical Papers, ISSCC 2006, session 31.6; and (2) Vital et al., A Concurrent Two-Step Flash Analogue-To-Digital Converter Architecture, ISCAS apos; 93, 1993 IEEE International Symposium, May 3-6, 1993, pp. 1196-1199, vol. 2.
These papers disclose a technique wherein the operational transconductance amplifiers (OTA) are shared between the several stages of the ADC. In an ordinary pipelined ADC implementation, the OTA is used only half of the time and is active for only half of each clock cycle. By sharing the OTA between two pipeline channels running in antiphase, or in opposite phases with one another, the OTA can be utilized all the time. Using the OTA all the time results in significant power dissipation savings. The principle of OTA sharing is shown in Gupta et al. while an actual implementation of a shared OTA is shown in Vital et al. This architecture that features OTA sharing is commonly called an “interleaved ADC.”
FIG. 2 shows an implementation of a single pipeline stage according to the interleaved ADC solution in accordance with one or more embodiments. In this implementation, the ADC consists of two parallel channels implemented in each pipeline stage. The inputs to the two channels are shorted such that the same signal is propagated through each channel. Alternatively, the two channels could be kept separate, implementing two parallel independent channels. The channels work in antiphase such that one channel is in hold mode when the other channel is in sampling mode.
The operation of the technique of OTA sharing implemented in a pipeline stage is as follows. The input signal to the stage is applied to two channels, 100 and 101. When the channel 100 starts in track-mode and channel 101 is in hold-mode, the input signal is applied to the sub-ADC 1 of channel 100 in parallel to a sampling network. The sub-ADC 1 quantizes the input signal and outputs N bits at the end of the track-phase. These N bits are converted back to an analog voltage by the DAC 2, to be used in the hold-phase. During the track-phase, all switches labeled “T” are closed. These switches are opened at the end of the track-phase sampling the input voltage on the sampling capacitors CS and CH. In the hold-phase, the switches labeled “H” are closed. This closes the loop around the amplifier comprising of the OTA input stage 3 and the OTA output stage 4, and the input voltage is amplified and held on the stage output terminal. The DAC output voltage is also subtracted from the output through the capacitive feedback network of CS and CH. This functionality is equal to an ordinary pipeline stage.
When the channel 100 is in the track-phase, the channel 101 may be in hold-phase. When the two channels switch phases, the OTA output stage 4 switches operation from one channel (e.g. 100) to the other (e.g. 101). Therefore, the OTA output stage 4 is active 100% of the time while it is idle during the track-phase of an ordinary pipeline stage. In FIG. 2, the OTA input stages 3, 3a will be idle during the track-phase of their respective channels 100, 101. However, in a typical implementation, most of the current from both channels 100, 101 flows through the OTA output stage 4, thereby providing the benefit of sharing the OTA output stage between the two channels 100, 101.
To further reduce power dissipation, it is possible to switch off the current in the OTA input stages 3 or 3a when the respective channel 100, 101 is in the track-phase. This would typically be implemented as a fixed bias current that is steered to one of the OTA input stages 3, 3a based on the clock signals controlling whether the channel 100, 101 is in track-phase or hold-phase. This would result in a bias current that is half of the bias current of a traditional solution.
A major challenge using such an OTA sharing principle is the generation of the necessary timing pulses for correct operation and accurate clocking of the pipeline stages. For high resolution ADCs, it is critical to generate a sampling clock with sufficiently low phase noise or equivalent clock jitter. In addition, in typical pipelined ADCs, the input clock may have exactly 50% duty cycle in order for the ADC to have full performance.
Therefore, there is a need for new timing circuits with specific characteristics to use with the architectures described above.